A 2.4 GHz Two Stage CMOS Class-F Power Amplifier for Wireless Applications

The design of a 2.4-GHz CMOS class-F power amplifier (PA) for wireless applications is presented in this paper. The class- F PA design is implemented using 0.13-μm CMOS process. It utilizes two stages cascade topology and the transistors are arranged in parallel to reduce the transistor’s on resistance which correspondingly increase the PA efficiency. The simulation results show that the PA delivers 12 dBm output power and 60% power added efficiency (PAE) into a 50 Ω load. The supply voltage is 1.3 V and the chip layout is 0.66 mm²